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Neuralink
South San Francisco, California, United States
Source: Neuralink careers · View original posting
From Neuralink's posting. “We” and “our” refer to the employer.
We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world.
The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.
We are looking for experienced and hands-on engineers with a creative and initiative mindset, who are interested in exploring the next-generation chip design with advanced architectures and hardware accelerators with a goal of enhancing the energy efficiency, information entropy, and scalability of our wireless brain-computer interfaces towards the physical limit of silicon technology. The ideal candidates are energetic people who get excited about building things, are highly analytical, and enjoy tackling new problems.
You will have the opportunity to collaborate closely with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team. As an Analog IC Layout Engineer, your responsibilities will include:
Base Salary Range: $83,000 — $139,000 USD
Full-time employees are eligible for the following benefits listed below.
Paid holidays
Commuter benefits
Meals provided
Equity (RSUs)
*Temporary Employees & Interns excluded
401(k) plan
*Interns initially excluded until they work 1,000 hours
Parental leave
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