IC/RTL Design Engineer

IC/RTL Design Engineer/ Front-End Engineer

About the role.

You design and implement the digital front-end RTL at the heart of the chip — including the high-speed datapath that moves data between UCIe and the optical front end. Guided by the interface specs and coding standards, you take blocks from micro-architecture through clean, timing-aware RTL and block-level verification. It's a hands-on role with room to grow your scope as the team and the chip mature.

What you'll do

• Develop block-level micro-architecture for your assigned blocks, and contribute to interface and register definitions.
• Design and implement front-end RTL blocks in SystemVerilog
• — datapath elements, the UCIe streaming/RDI adapter, elastic FIFOs, and supporting logic.
• Integrate IP and support parameterization for configurability.
• Write clean, lint-clean, CDC/RDC-clean RTL that follows the coding and quality standards.
• Write block-level testbenches, sanity checks, and assertions (SVA) for your own blocks before handoff to DV.
• Power- and timing-aware design
• — managing block activity, clock-gating, pipelining, and retiming; partner with the backend team on physical closure for your blocks.
• Bring-up and debug across simulation and emulation / FPGA prototyping; support DV and silicon bring-up, including DFT/debug hooks in your blocks.
• Collaborate with the architecture, modelling, DV, DFT, and backend teams as your blocks move through the flow.
• Required
• BS or MS in Electrical/Computer Engineering
• (or equivalent experience).
• 3+ years of digital RTL design in SystemVerilog
• , with blocks taken from micro-architecture through to verification handoff.
• Solid digital design fundamentals
• : pipelining, FSMs, FIFOs, clock-domain crossing, and streaming/bus interfaces (e.g., AXI).
• Lint and CDC/RDC discipline and clean-RTL practices.
• Power- and timing-aware design practices; comfort with synthesis and timing closure, working with the backend team.
• Strong debug skills in simulation
• ; scripting in Python, Perl, or TCL.
• Preferred
• High-speed datapath, SerDes-adjacent, or interface design exposure