Responsibilities
THE ROLE:
Be part of AMD’s analog/mixed signal IP design team responsible for the design and development of next generation IOs, high speed memory (LPDDRx, gDDRx, HBMx) and die-to-die Gbps proprietary PHY IP solutions. Establishes and maintains AMD’s technological leadership position in analog circuit architecture and design with a proven track record for problem solving and innovation.
THE PERSON:
The ideal candidate has excellent experience in technical settings. You also have excellent communication, writing, and presentation skills.
KEY RESPONSIBLITIES:
High Speed IO/SerDes AMS circuit architecture and design
Work and collaborate with System/Platform & SOC architects to translate system level specs to AMS blocks/circuit level specifications.
Author AMS blocks circuit and architecture technical specifications, AMS pre-silicon verification, AMS post-silicon characterization/validation test plans.
PREFERRED EXPERIENCE:
Hand-on design experience in multi-Gbps serial (PCIE, USB, …), parallel high BW memory interface PHY/IOs (DDR4/DDR5, HBM2/HBM3, gDDR5/gDDR6, …) and chip-to-chip links PHY IPs
Strong fundamentals and knowledge of mixed signal circuit architecture and design techniques for receiver/transmitter and PLL/DLL/clocking. In-depth knowledge of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniques
Solid experience of designing and architecting analog mixed-signal circuit blocks including DLLs, phase interpolator, low jitter clock distribution, bandgap, biasing circuits, LDO regulators, amplifiers, comparators. Experience in mixed signal design circuit blocks such as digital/analog DLLs, duty cycle corrector, clock and data recovery, clock mixer, …
Solid Understanding of high-speed IO signaling topologies and architectures including system-silicon co-design/co-optimizations for best in class PPA.
Solid understanding of high speed IO link budget analysis and jitter/SNR metrics and design trades.
Experience in low power design techniques for high speed/custom digital circuit (e.g. CMOS/CML high speed design for counters, dividers, …) design and analysis including transistor level timing sign-off
- Solid understanding of power, area and performance trade-offs in mixed signal IP design
- Design Experience in FinFet advanced CMOS process nodes 16nm/7nm/3nm and below coupled with a solid understanding of transistor device performance and fundamentals
- Proficient in AMS design flows, tools, and methodologies. Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools
- Work with project-manager, system architects, IC designers and physical designers to guarantee quality/timely deliverables meeting project’s schedule and technical requirements
Analytical thinking, inventive, and Quality-oriented mindset. Strong and effective technical and management communication at the peer and upward management levels.
Track record of successfully taking AMS designs to production
ACADEMIC CREDENTIALS:
MS or PhD in Electrical, Computer Engineering or related equivalent
LOCATION:
San Jose, CA
This role is not eligible for visa sponsorship.
Qualifications
