layiq

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worthy; deserving; fitting; suitable.

A role, opportunity, or path that merits attention, time, and pursuit.

Senior SoC Power Modeling Engineer at AMD | LAYIQ

SoC & Use‑Case Power Modeling
Develop and maintain SoC-level power models for Embedded x86 platforms using IP-level inputs (CPU, GPU, fabric, memory, and I/O).
Create use-case-driven power models representing automotive, industrial, edge computing, and customer-specific embedded workloads.
Translate real-world workloads into model inputs such as activity factors, concurrency, residency, and DVFS states.
Power‑Frequency & Electrical Modeling
Build and maintain Voltage‑Frequency (VF) curves across operating corners.
Derive and validate EDC / TDC / current limits based on modeled workloads and platform constraints.
Perform sensitivity studies across frequency, voltage, workload mix, and power states.
IP‑to‑SoC Model Integration
Integrate IP‑level power models into cohesive SoC‑level frameworks.
Ensure consistency of assumptions across IPs (clocking, power states, gating, DVFS).
Identify gaps, inconsistencies, or inaccuracies in IP models and drive closure with IP teams.
Architecture & Trade‑off Analysis
Partner with SoC and power architects to influence early architectural decisions.
Evaluate power/performance/area trade‑offs for new features, configurations, and SKUs.
Support bounding‑box analysis and product positioning decisions.
Correlation & Continuous Improvement
Support pre‑silicon to post‑silicon correlation of power models.
Refine models using silicon data, profiling, and validation feedback.
Improve modeling methodologies, accuracy targets, and documentation.
PREFERRED EXPERIENCE: Professional experience in power modeling, power estimation, or SoC power analysis
Strong understanding of: SoC power architecture and DVFS
Static vs dynamic power components
EDC / TDC / electrical and thermal constraints
Hands‑on experience building
SoC‑level power models from
IP‑level models
Experience creating and analyzing
VF curves
Experience with Embedded or Automotive SoCs
Familiarity with x86 CPU, GPU, memory, and fabric power behaviors
Exposure to power modeling tools, spreadsheets, or internal frameworks used for pre‑silicon estimation
Experience with workload‑driven modeling and benchmark abstraction
Strong analytical and scripting skills (Python preferred)
Ability to work across architecture, IP, performance, and validation teams
Prior involvement in power correlation with silicon
Ability to clearly communicate modeling assumptions and results to senior technical stakeholders
ACADEMIC CREDENTIALS: BS/MS in Electrical Engineering, Computer Engineering, or related field
LOCATION: Austin, TX
This role is not eligible for visa sponsorship.

Responsibilities

THE ROLE:

We are seeking a Senior Power Modeling Engineer to drive pre-silicon power modeling and analysis for AMD’s next-generation
Embedded x86 SoC platforms
. This role plays a critical part in defining use-case-driven power expectations

, building

SoC-level power models from IP inputs

, and enabling informed

EDC/TDC, voltage-frequency (VF), and PPA trade-off decisions early in the design cycle.

THE PERSON:

The ideal candidate brings deep hands-on experience with SoC power modeling methodologies and understands how IP-level power characteristics scale to full-chip behavior. This engineer will collaborate closely with SoC architects, power architects, performance teams, and silicon validation teams to ensure accurate power projections and influence architectural direction.

KEY RESPONSIBILITIES:

SoC & Use‑Case Power Modeling
Develop and maintain SoC-level power models for Embedded x86 platforms using IP-level inputs (CPU, GPU, fabric, memory, and I/O).
Create use-case-driven power models representing automotive, industrial, edge computing, and customer-specific embedded workloads.
Translate real-world workloads into model inputs such as activity factors, concurrency, residency, and DVFS states.
Power‑Frequency & Electrical Modeling
Build and maintain Voltage‑Frequency (VF) curves across operating corners.
Derive and validate EDC / TDC / current limits based on modeled workloads and platform constraints.
Perform sensitivity studies across frequency, voltage, workload mix, and power states.
IP‑to‑SoC Model Integration
Integrate IP‑level power models into cohesive SoC‑level frameworks.
Ensure consistency of assumptions across IPs (clocking, power states, gating, DVFS).
Identify gaps, inconsistencies, or inaccuracies in IP models and drive closure with IP teams.
Architecture & Trade‑off Analysis
Partner with SoC and power architects to influence early architectural decisions.
Evaluate power/performance/area trade‑offs for new features, configurations, and SKUs.
Support bounding‑box analysis and product positioning decisions.
Correlation & Continuous Improvement
Support pre‑silicon to post‑silicon correlation of power models.
Refine models using silicon data, profiling, and validation feedback.
Improve modeling methodologies, accuracy targets, and documentation.
PREFERRED EXPERIENCE: Professional experience in power modeling, power estimation, or SoC power analysis
Strong understanding of: SoC power architecture and DVFS
Static vs dynamic power components
EDC / TDC / electrical and thermal constraints
Hands‑on experience building
SoC‑level power models from
IP‑level models
Experience creating and analyzing
VF curves
Experience with Embedded or Automotive SoCs
Familiarity with x86 CPU, GPU, memory, and fabric power behaviors
Exposure to power modeling tools, spreadsheets, or internal frameworks used for pre‑silicon estimation
Experience with workload‑driven modeling and benchmark abstraction
Strong analytical and scripting skills (Python preferred)
Ability to work across architecture, IP, performance, and validation teams
Prior involvement in power correlation with silicon
Ability to clearly communicate modeling assumptions and results to senior technical stakeholders
ACADEMIC CREDENTIALS: BS/MS in Electrical Engineering, Computer Engineering, or related field
LOCATION: Austin, TX
This role is not eligible for visa sponsorship.

Senior SoC Power Modeling Engineer

Employer job description

WHAT YOU DO AT AMD CHANGES EVERYTHING

THE ROLE:

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Benefits offered are described:

Responsibilities

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