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AMD
San Jose, California
Source: AMD careers · View original posting
From AMD's posting. “We” and “our” refer to the employer.
As ASIC Director – Chip Lead in our Product Development team, you will be responsible for providing technical leadership to one or more Adaptive & Embedded Computing Group (AECG) device programs. You will have sign-off responsibility for the technical execution of device programs from conception & planning to release to manufacturing.
Your leadership responsibilities will focus on problem solving in all aspects of the device development cycle including architecture, RTL, analog & custom design, design for test & manufacturing, verification, physical design & timing closure, physical verification, tapeout and post-silicon validation & qualification. When a problem does not clearly fall under the banner of one technical team or another it becomes the responsibility of the Chip Lead to bring expertise, experience and diplomacy together to coordinate a solution.
This position requires a wide breadth of understanding of and experience with ASIC design and development. It also requires strong interpersonal skills to resolve issues between highly skilled and experienced engineering colleagues. A successful candidate will work with senior silicon design engineers, architects, and micro-architects from a wide variety of technical teams. The candidate will be attuned to the overall goals and objectives of the program and employ excellent communication and problem-solving skills.
As ASIC Director – Chip Lead in our Product Development team, you will be responsible for providing technical leadership to one or more Adaptive & Embedded Computing Group (AECG) device programs. You will have sign-off responsibility for the technical execution of device programs from conception & planning to release to manufacturing.
Your leadership responsibilities will focus on problem solving in all aspects of the device development cycle including architecture, RTL, analog & custom design, design for test & manufacturing, verification, physical design & timing closure, physical verification, tapeout and post-silicon validation & qualification. When a problem does not clearly fall under the banner of one technical team or another it becomes the responsibility of the Chip Lead to bring expertise, experience and diplomacy together to coordinate a solution.
This position requires a wide breadth of understanding of and experience with ASIC design and development. It also requires strong interpersonal skills to resolve issues between highly skilled and experienced engineering colleagues. A successful candidate will work with senior silicon design engineers, architects, and micro-architects from a wide variety of technical teams. The candidate will be attuned to the overall goals and objectives of the program and employ excellent communication and problem-solving skills.
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