Responsibilities
THE ROLE:
As the semiconductor industry pivots toward complex chiplet architectures and hyper-dense data center accelerators, the economics of quality necessitate shifting validation earlier in the production lifecycle. We are seeking a visionary
Lead/Principal Diagnostics Engineer to drive our shift from proven post-silicon software validation frameworks and System-Level Tests (SLT) directly into Automated Test Equipment (ATE) and Wafer Sort environments.
THE PERSON:
In this role, you will bridge the gap between platform-level software execution and traditional hardware-driven manufacturing test patterns. You will design the architecture, tooling, and translation methodologies required to pack, convert, and stream complex software-driven GFX and compute test cases into robust, production-grade ATE patterns. This is a high-impact role requiring deep knowledge of system software/hardware interactions, graphics IP mechanics, and high-volume structural/functional manufacturing test domains.
KEY RESPONSIBILTIIES
Strategic Technical Leadership:
Define the technical roadmap, architecture, and deployment strategy for migrating post-silicon SLT and functional GFX IP feature diagnostics onto wafer sort and ATE hardware configurations.
Pattern Generation & Conversion:
Architect and develop software utilities/pipelines to convert functional diagnostic sequences, register configurations, and compute workloads into cycle-accurate vector formats (e.g., STIL, WGL, or proprietary tester formats) compatible with high-end ATE testers.
Cross-Domain Collaboration:
Serve as the primary technical liaison between the GFX/Compute Diagnostics team, Product/Test Engineering, and Design-for-Test (DFT) teams
Platform Integration & Emulation:
Analyze existing platform-level hardware/software dependencies (such as sideband management interfaces, firmware, and power management behaviors) to build deterministic, tester-friendly models that emulate host behaviors on ATE hardware.
Test Coverage & Cost Optimization:
Optimize tester execution times (test cost reduction) while maximizing structural and functional test coverage for data center GPU IPs, focusing on massively parallel compute pipelines, high-bandwidth memory (HBM) controllers, and matrix math engines.
PREFERRED EXPERIENCE:
Experience:
Proven industry experience in silicon engineering spanning post-silicon validation, product engineering, diagnostics development, or structural/functional test generation.
Platform HW/SW Proficiency:
Strong programming background in C/C++ and Python, with a concrete understanding of bare-metal or driver-level programming, registers, firmware interactions, and system memory maps.
ATE Knoweldge:
Proven hands-on experience with production-grade Automated Test Equipment platforms (e.g., V93000, UltraFLEX) and structural/functional testing at the wafer sort or final test level.
Pattern Flow Knowledge:
Expert understanding of structural pattern generation, vector timing, clock domains, and diagnostic patterns (such as functional vectors, BIST/MBIST, or scan compression output).
Familiarity with high-volume manufacturing challenges unique to data center architectures, including high-power profiles, HBM integration, and multi-die chiplet interconnect protocols (e.g., UCIe, proprietary fabrics).
Deep understanding of GFX and compute architectures, with proven ability to design and implement diagnostic and test cases that maximize coverage and proactively identify silicon issues early
- Understanding of AI/ML principles and some experience in applying LLM & ML models in applications
- Experience with working in DevOps environment like GitHub, CI/CD pipelines
- Excellent problem-solving abilities with a keen eye for detail are highly valued
ACADEMIC CREDENTIALS:
Education:
Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
LOCATION:
Austin,TX
This role is not eligible for visa sponsorship.
Qualifications
