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AMD
San Jose, California
Source: AMD careers · View original posting
From AMD's posting. “We” and “our” refer to the employer.
Join our leading-edge
RTL Design Methodology team as a Hardware Development Engineer
, where you will contribute to the development of next-generation FPGA products. In this role, you will help define and improve the methodologies and tools that enable high-quality RTL design across our engineering organization.
Working closely with RTL designers and verification engineers, you will support the deployment and improvement of front-end design and static verification flows that ensure robust, high-quality silicon. This is an excellent opportunity to build deep expertise in advanced FPGA development while contributing to methodologies used across the company.
You are an early-career RTL or design methodology engineer who enjoys solving complex technical problems and learning new tools and flows. You thrive in a fast-paced engineering environment and are motivated by the opportunity to improve design productivity and quality.
You are comfortable working on a small, highly capable team where initiative and ownership are valued, and you enjoy collaborating with design and verification teams to continuously improve engineering processes.
We will guide you as you ramp up on our RTL design and static verification tools and methodology ecosystem.
Collaborate with the design team to drive continuous improvements in front-end design methodologies, ensuring top-quality RTL across areas such as Lint, CDC, formal equivalence, and low-power verification.
Leverage corporate AI systems to increase productivity and streamline workflows.
Experience in logic design and static verification (SystemVerilog, Verilog, or VHDL).
Strong background in RTL/logic design.
Programming skills in Perl, Python, and TCL.
Bachelor's degree in Electrical or Computer Engineering; Master's or PhD degree preferred.
San Jose, CA
This role is not eligible for visa sponsorship.
Join our leading-edge
RTL Design Methodology team as a Hardware Development Engineer
, where you will contribute to the development of next-generation FPGA products. In this role, you will help define and improve the methodologies and tools that enable high-quality RTL design across our engineering organization.
Working closely with RTL designers and verification engineers, you will support the deployment and improvement of front-end design and static verification flows that ensure robust, high-quality silicon. This is an excellent opportunity to build deep expertise in advanced FPGA development while contributing to methodologies used across the company.
You are an early-career RTL or design methodology engineer who enjoys solving complex technical problems and learning new tools and flows. You thrive in a fast-paced engineering environment and are motivated by the opportunity to improve design productivity and quality.
You are comfortable working on a small, highly capable team where initiative and ownership are valued, and you enjoy collaborating with design and verification teams to continuously improve engineering processes.
We will guide you as you ramp up on our RTL design and static verification tools and methodology ecosystem.
Collaborate with the design team to drive continuous improvements in front-end design methodologies, ensuring top-quality RTL across areas such as Lint, CDC, formal equivalence, and low-power verification.
Leverage corporate AI systems to increase productivity and streamline workflows.
Experience in logic design and static verification (SystemVerilog, Verilog, or VHDL).
Strong background in RTL/logic design.
Programming skills in Perl, Python, and TCL.
Bachelor's degree in Electrical or Computer Engineering; Master's or PhD degree preferred.
San Jose, CA
This role is not eligible for visa sponsorship.
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