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Alice & Bob
Paris
Source: Alice & Bob careers · View original posting
From Alice & Bob's posting. “We” and “our” refer to the employer.
Alice & Bob is developing the first universal, fault-tolerant quantum computer to solve the world’s hardest problems.
The quantum computer we envision building is based on a new kind of superconducting qubit: the Schrödinger cat qubit
🐈⬛
. In comparison to other superconducting platforms, cat qubits have the astonishing ability to implement quantum error correction autonomously!
We're a diverse team of 250+ brilliant minds from over 35 countries united by a single goal: to revolutionise computing with a practical fault-tolerant quantum machine. Are you ready to take on unprecedented challenges and contribute to revolutionising technology? Join us, and let's shape the future of quantum computing together!
Alice & Bob's current 48-qubit generation was hand-drawn — the next generations won't be. As we scale toward 1,000-, 10,000-, and eventually million-qubit chips, manual layout stops being an option: it doesn't scale, and it caps how fast we can iterate. This role exists to build the infrastructure — PDK, generators, automated flows — that lets chip complexity grow 10–1,000× while design cycle time stays flat.
You'll build the layout infrastructure that makes that scaling possible — PDK, layout compilers, parasitic extraction, hierarchical verification, and mask generation. This is a semiconductor physical-design role applied to superconducting hardware, not a quantum physics one.
Responsibilities: Build and own the PDK — layer stack, technology file, parametric cells (junctions, CPW, resonators, couplers, pads, airbridges/crossovers) — and their DRC/LVS decks
Requirements: 5+ years in physical design, custom/analog layout, PDK development, or mask data prep in a semiconductor context (CMOS backend, RF/analog, MEMS, or photonics), including at least one production tape-out owned end-to-end
Track record scaling a layout methodology — replacing hand-drawn layout with generators, PCells, or hierarchical flows on a design that grew substantially in element count
Hands-on parasitic extraction experience — commercial (Calibre xRC/xACT, Quantus, StarRC) and/or field-solver-based (FastCap/FastHenry, BEM/FEM) — including deck/rule-file development and correlation against EM or measurement
Nice to Have
Experience with superconducting or cryogenic device layout (Nb/Ta/TiN/Al thin films, Josephson junctions, CPW resonators, airbridges) and the loss/crosstalk-driven layout rules that come with it
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