layiq

/la·yiq/adjective

worthy; deserving; fitting; suitable.

A role, opportunity, or path that merits attention, time, and pursuit.

Semiconductor Packaging Integration Research Manager at Intel | LAYIQ

Lead packaging integration research programs focused on heterogeneous integration, chiplets, 2.5D/3DIC, hybrid bonding, wafer-level packaging, and emerging die-to-die interconnect technologies.
Define integration research strategy, technical roadmaps, research milestones, and decision criteria aligned to future product, platform, and system-level scaling requirements.
Manage multidisciplinary team of integration researchers, packaging technologists, process integration engineers, modeling experts, design, and technical program leads.
Translate system requirements into package integration solutions by balancing performance, power, area, latency, bandwidth, thermal behavior, mechanical stress, reliability, cost, and manufacturability.
Partner with silicon design, device, process, substrate, assembly, test, reliability, thermal, signal integrity, power delivery, failure analysis, and manufacturing teams to close cross-domain integration gaps.
Drive feasibility studies, architecture trade-off analysis, process module evaluation, design rule development, prototyping, design-of-experiments, and experimental validation for new integration concepts.
Lead technology readiness assessments, integration risk reviews, failure analysis learning cycles, reliability evaluations, and manufacturing feasibility reviews for early-stage packaging options.
Drive intellectual property, technical publications, competitive benchmarking, and internal knowledge transfer related to advanced packaging integration.
Guide research-to-development transfer by defining integration requirements, qualification gaps, process control needs, manufacturability risks, cost implications, and scaling paths.
Communicate technical progress, trade-offs, risks, investment needs, and strategic recommendations to senior technical and business leaders.
Key Competencies
Si-Package co-optimization across process, integration, electrical, thermal, mechanical, reliability, manufacturability, and cost dimensions
Advanced packaging integration research leadership and technical vision
Heterogeneous integration, chiplet, 2.5D/3DIC, hybrid bonding, and emerging interconnect expertise
Technology pathfinding, roadmap definition, research portfolio management, and research-to-development transfer
Modeling, simulation, prototyping, experimentation, failure analysis, and data-driven integration learning
Cross-disciplinary influence across device, design, process, materials, test, reliability, thermal, electrical, and manufacturing teams
External ecosystem collaboration with universities, consortia, suppliers, and equipment vendors
Strategic communication, risk framing, and executive-level technical storytelling
Required Skills and Experience
Demonstrated experience leading advanced technology research programs, multidisciplinary technical teams, cross-functional initiatives, or external research collaborations.
Ability to convert ambiguous integration challenges into clear hypotheses, experimental plans, measurable milestones, technology readiness criteria, and actionable recommendations.
Strong understanding of package-system integration, chiplet architectures, advanced interconnects, substrates, interposers, assembly materials, wafer-level processes, thermal-mechanical behavior, power delivery, signal integrity, reliability, and manufacturability trade-offs.
Strong communication skills with the ability to present complex technical findings, integration trade-offs, risks, and recommendations to executive, technical, and cross-functional audiences.
Preferred Skills and Experience
Strong record of innovation in semiconductor packaging integration, heterogeneous integration, chiplet architectures, 2.5D/3DIC, hybrid bonding, interposer technology, fan-out, wafer-level packaging, substrate technology, or package-system co-optimization.
Experience with research-to-development transfer, technology readiness frameworks, pathfinding, prototype builds, process integration learning, and early manufacturing feasibility assessment.
Knowledge of thermal-mechanical modeling, warpage, stress, CTE mismatch, electromigration, reliability physics, high-speed I/O, power integrity, signal integrity, die-to-die interfaces, and package-level co-design.
Demonstrated record of patents, publications, conference presentations, industry consortia participation, university research collaboration, or external ecosystem leadership.
Experience leading multi-organization collaborations with suppliers, equipment vendors, universities, research labs, OSATs, foundry partners, design teams, or customer technology teams.
Familiarity with AI, HPC, data center, automotive, mobile, networking, edge computing, advanced memory, or custom silicon packaging requirements.

Semiconductor Packaging Integration Research Manager

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