CPU Full-chip Physical Integration Engineer

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Apple’s Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level implementation.

Description

As a Full Chip Integration Engineer, you will be participating in the physical design, integration, and verification of high performance, low power processor development.

• Full chip floorplan, area optimizations, block partitioning and pin placements
• Own chip level place and route (PnR), final CPU layout database construction and verification (PDV)
• Develop and validate Power Grid, including routability analysis
• Drive custom layout integration, block and full-chip level EM/IR, electrical verification/analysis as well as formal verification
• Work with the implementation/CAD teams during the entire chip design cycle to drive signoff closure for tapeout
• Work with the SOC team to meet IP technical and delivery requirements
• Participate in establishing CAD and physical design methodologies and flow development for chip integration and analysis
• Scripting to automate tasks and improve debug efficiency

Minimum Qualifications

• Minimum BS and 10+ years of relevant industry experience
• Experience with scripting in Perl or TCL

Preferred Qualifications

• Knowledge of industrial standards and practices in Physical Design, including Floorplanning, Partitioning, Budgeting, Place and Route and Physical Verification
• Experience in developing and implementing Power Grid and Clock specifications
• Solid knowledge of Low Power Design, Physical Construction, Integration, EMIR (Drop/Noise), SIGEM Analysis, Formal Verification, Physical PDV, DRC/LVS Verification, and DFM