Design Verification Engineer

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Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Responsible for verifying complex digital IPs. Work with the system architects and digital designers, making block level specifications clear and precise. Use the specifications to build verification plans to exercise the functional, performance, stress cases, and error conditions. Own the creation of the verification test benches using formal verification and UVM based simulation.

Build the test cases using System Verilog Assertions and constrained random UVM testcases to get complete functional and code coverage for your blocks. Participate in code reviews of other blocks in the chips, offering proposals to more efficiently achieve bug free designs on the first tape out. Collaborate in developing precise design specifications for digital control blocks. Use design specifications to create block and chip level verification plans. Architect and create block level verification elements.