FE Engineering

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Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Work on timing closure aspect of ASIC chips in deep sub-micron process. Responsible for SoC (System-on-Chip) design effort interfacing with all disciplines. Develop and enhance timing constraints for a complex, multi-clock and multi-voltage SoC. Develop timing constraint and coverage analysis scripts and checks. Develop and enhance timing related scripts for critical path analysis, and various hard macro interfaces.

Develop full chip as well as block level constraints for multiple timing modes. Work on timing closure of I/O interfaces. Full chip and block level timing closure ownership throughout the entire project cycle (RTL, synthesis and physical implementation). Develop and maintain methodology and flows related to timing verification and closure. Generation of block and full chip timing constraints. Work on Apple SoC chips in deep sub-micron technologies targeted for high end mobile applications.