FE Engineering

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Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Deliver complex digital IPs for Power Management ICs (PMICs), meeting schedule, area, power, and performance targets. Perform RTL design in SystemVerilog for digital control logic, including the implementation of FSMs and other control structures. Collaborate with cross-functional teams, including Analog Design, Architecture, DFT, and ATE, to develop and finalize precise design specifications.

Synthesize RTL designs into gates and analyze Power, Performance, and Area (PPA) impact using industry-standard tools such as Synopsys Design Compiler, Cadence Genus, and PrimeTime PX. Apply low-power design techniques, including clock and power gating. Perform RTL simulation and functional verification using tools like Cadence Xcelium and Simvision to assess waveforms and ensure correct functionality. Collaborate with the verification team to ensure RTL code meets all feature requirements as defined in the specifications.