layiq

/la·yiq/adjective

worthy; deserving; fitting; suitable.

A role, opportunity, or path that merits attention, time, and pursuit.

ASIC/FPGA Design and Verification Engineer – Space Electronics – (Senior or Principal) - MTV at The Boeing Company | LAYIQ

Conduct unit-level testing, verification, and validation of embedded software and firmware, utilizing debugging tools like oscilloscopes and logic analyzers to identify and resolve issues.
Create and maintain technical documentation, including requirements documents, design specifications, test plans, and interface control documents.
Support the integration of software and hardware components, from initial hardware bring-up to final system validation.
Analyze and enhance the efficiency, stability, scalability, and performance of system resources, often within the constraints of low power or memory.
Position Responsibilities: Lead FPGA/ASIC designs, including multi-FPGA/ASIC programs and teams with design and verification engineers, and manage team execution to meet program milestones
Collaborate with customers, system engineers, and hardware engineers to drive requirements capture and architect digital logic functions to meet mission/customer needs
Explore trade-space of potential ASIC/FPGA technologies and determine the optimal parts, weighing Schedule, Cost, Risk, Area, Power (SCRAP) vs. performance
Implement FPGA/ASIC with latest design practices and tools from block-level micro-architecture, through HDL coding, and physical design realization (through gate-level netlists for ASIC designs)
Integrate DSP IP from Boeing’s algorithm team and third-party IP as needed
Perform static timing analysis, LEC, CDC, linting, and other necessary checks to ensure the design is completed on schedule
Develop Functional Coverage Models and perform Code Coverage to verify designs in simulation
Create self-checking and reusable test benches from scratch, applying Object Oriented Programming concepts such as Inheritance and Polymorphism, and leverage UVM to create drivers, monitors, predictors, and scoreboards
Drive FPGA-based prototyping and validation depending on program and system requirements and complexity
Validate design through hardware integration test with special test equipment, test-beds, and higher-level systems as needed
Train and mentor less senior engineers across the department and help build effective project teams
This position is expected to be 100% onsite. The selected candidate will be required to work onsite at the listed location.

Principal, Level 6: 20+ years of related work experience or an equivalent combination of education and experience
Master's Degree in EE, Computer Engineering/Science, or related field, or equivalent experience
Proven record of leading ASIC/FPGA design and/or verification teams, including tracking and reporting progress to stakeholders
Experience with hardware emulators, especially Palladium
Proficiency with hardware verification languages: System Verilog, System Verilog Assertions
Ability to executable test plans
Proficiency with Object Oriented Programming Concepts: Inheritance, Polymorphism, etc.
Ability to create self-checking and reusable testbenches from scratch
Experience developing Functional Coverage Models and Closing Code Coverage
Experience with high-speed Serdes interfaces (JESD204C, PCIe, Ethernet)
Proficient in scripting languages: Make, Perl, Python, etc.
Revision Control Systems: svn, cvs, git
Proficient in Linux Environments
Familiarity with space-based design techniques and radiation mitigation
Demonstrated history of 1st pass success with ASIC designs
Conflict of Interest: Successful candidate for this job must satisfy the Company’s Conflict of Interest (COI) assessment process.
Typical Education/Experience: Senior (Level 5): Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), computer science, engineering data science, mathematics, physics or chemistry (e.g. Bachelor) and typically 14 or more years' related work experience or an equivalent combination of technical education and experience or non-US equivalent qualifications. In the USA, ABET accreditation is the preferred, although not required, accreditation standard.
Principal (Level 6): Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), computer science, engineering data science, mathematics, physics or chemistry (e.g. Bachelor) and typically 20 or more years' related work experience or an equivalent combination of technical education and experience or non-US equivalent qualifications. In the USA, ABET accreditation is the preferred, although not required, accreditation standard
Relocation: This position offers relocation based on candidate eligibility. Note: Basic relocation will be offered for eligible internal candidates.
Drug Free Workplace: Boeing is a Drug Free Workplace where post offer applicants and employees are subject to testing for marijuana, cocaine, opioids, amphetamines, PCP, and alcohol when criteria is met as outlined in our policies .
Shift Work Statement: This position is for 1st shift.

ASIC/FPGA Design and Verification Engineer – Space Electronics – (Senior or Principal) - MTV

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