Responsibilities
THE ROLE:
Join a team developing next-generation AI and high-performance computing silicon. In this role, you will lead and contribute to advanced-node physical design for complex ASIC and SoC products, driving implementation, timing closure, signoff, and design optimization across block, subsystem, and chip-level designs.
Working closely with architecture, RTL, CAD, technology, and product engineering teams, you will help deliver high-quality silicon while advancing methodology, automation, and data-driven design solutions that improve power, performance, and area (PPA).
THE PERSON:
You are a hands-on physical design expert with a strong track record of solving complex implementation and timing challenges on advanced-node designs. You combine deep technical expertise with the ability to provide technical leadership, influence design decisions, mentor engineers, and collaborate effectively across globally distributed teams. You are detail-oriented, highly analytical, and thrive in fast-paced environments where ownership and innovation are valued.
KEY RESPONSIBLITIES:
Lead physical design activities across block, subsystem, and chip-level implementations.
Drive timing closure, signoff readiness, and PPA optimization for advanced-node designs.
Develop and enhance physical design methodologies, design flows, and automation solutions.
Perform static timing analysis, variation-aware timing analysis, and clock-tree optimization.
Define and execute engineering change (ECO) strategies throughout implementation and signoff.
Support formal verification, physical verification, and tapeout preparation activities.
Analyze design data and trends to improve design quality, predictability, and efficiency.
Collaborate with cross-functional engineering teams to achieve successful silicon delivery.
Contribute to AI-assisted and machine learning-driven design optimization initiatives.
Troubleshoot complex implementation challenges and develop scalable technical solutions.
PREFERRED EXPERIENCE:
Experience with ASIC physical design, implementation, and timing closure.
Experience working across block, subsystem, and chip-level design environments.
Strong knowledge of static timing analysis, clock-tree synthesis, signoff, and ECO methodologies.
Experience with industry-standard implementation tools such as Synopsys ICC2, Fusion Compiler, and/or Cadence Innovus.
Experience with timing, power, and signoff tools such as PrimeTime, PrimeTime PX, PrimeShield, RedHawk, Formality, or Conformal.
Advanced-node semiconductor design experience, including leading-edge process technologies.
Strong scripting and automation skills using TCL, Python, Perl, Pandas, or similar technologies.
Experience developing design flows, methodologies, and productivity-enhancing automation.
Exposure to machine learning, AI-assisted design optimization, or data-driven engineering workflows.
Experience with data analysis, database technologies, and design-quality metrics.
ACADEMIC CREDENTIALS:
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field preferred.
This role is not eligible for visa sponsorship.
Qualifications
