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Loading LAYIQ…From Apple's posting. “We” and “our” refer to the employer.
Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.
Description
APPLE INC has the following available in Austin, Texas. Responsible for Logic Synthesis for Apple GFX Partitions. Responsible for LEQ/ATPG/DFT/Lint clean designs. Run various experiments to help in achieving the best design QoR metrics (Power, Performance, Area). Work closely with the RTL and PD (physical design) teams. Responsible for synthesis, analysis, and optimization of the delivered IP.
Use and develop advanced techniques spanning RTL/Synthesis/Place and Route to meet challenging timing, power and area targets while also working with our partners in STA and DFT to achieve successful first silicon. Implement logically coded (RTL) design with technology specific silicon netlist with product area, power and performance goals with required design validation checks performed.
Run various synthesis trials in industry tools and analyze the reports to improve power, performance and area of the design owned as part of Apple Graphics team. Collaborate with IP team and Physical design team to address design issues and generate ideas to enhance the design. Ensure the synthesized netlist is power clean, logically equivalent and Lint clean and has the best quality of result. Ensure that the DFT (Design for Test) chains are successfully inserted in all the designs with good test coverage.
Debug issues and suggesting solutions collaborating with vendors and CAD (Computer Aided Design) support teams. Explore possibilities to automate the existing flows and explore the possibilities of creating utilities which can assist in improving design quality. Perform ECO’s to address changes on the netlist post release. Perform signoff checks at the end of design cycle to ensure that the design meets acceptable criteria and quality. 40 hours/week.
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