layiq
/la·yiq/adjective
worthy; deserving; fitting; suitable.
A role, opportunity, or path that merits attention, time, and pursuit.
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Job opportunity
ASIC Design Engineer - Digital DSP Design & Analog/Mixed-Signal
Celero Communications, Inc.
Irvine, CA
Source: Celero Communications, Inc. careers · View original posting
- Pay
- Annual Base Salary Range for US: $150,000 - $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)
Employer job description
From Celero Communications, Inc.'s posting. “We” and “our” refer to the employer.
ASIC Design Engineer
Celero Communications is an exciting and fast-growing semiconductor startup developing innovative technologies that power next-generation AI and data center infrastructure. Our products enable high-performance optical connectivity and next-generation optical transceivers and modems.
Celero is seeking a highly skilled and motivated ASIC Design Engineer to join our team and contribute to the development of advanced ASICs for high-speed optical communication systems. The ideal candidate will have strong digital ASIC design expertise combined with hands-on experience in DSP, Analog, and/or SerDes technologies.