layiq
/la·yiq/adjective
worthy; deserving; fitting; suitable.
A role, opportunity, or path that merits attention, time, and pursuit.
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Job opportunity
Principal PLL Design Engineer
Celero Communications, Inc.
Irvine, CA or San Jose, CA
Source: Celero Communications, Inc. careers · View original posting
- Pay
- Annual Base Salary Range for US: $150,000 - $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)
Employer job description
From Celero Communications, Inc.'s posting. “We” and “our” refer to the employer.
Are you a PLL Design Engineer passionate about developing the high-speed clocking technology that will power the next generation of AI infrastructure? Join our fast-growing semiconductor startup and help deliver disruptive High-Speed Interconnect solutions for tomorrow's optical networks.
We are seeking a High-Speed CMOS PLL Analog Design Engineer to play a key role in the architecture and design of advanced clocking circuits for next-generation optical transceivers, high-speed SerDes, and high-performance ADC/DAC systems. In this role, you will architect and design state-of-the-art PLLs for industry-leading transceivers, working alongside a world-class team to solve some of the most challenging mixed-signal design problems in advanced CMOS technologies.