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Santa Clara, California
Source: AMD careers · View original posting
From AMD's posting. “We” and “our” refer to the employer.
ADVANCE YOUR CAREER. ADVANCE THE WORLD.
At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.
Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.
The Circuit Technology team is looking for an experienced DFT/DFx Methodology, Architecture, and RTL Execution Lead to support high-speed SerDes PHYs, next-generation Memory PHYs, and die-to-die interconnect IPs.
In this role, you will own and lead DFT/DFx architecture definition, RTL implementation, methodology development, scan integration support, test constraints, ATPG support, and post-silicon debug for advanced PHY and connectivity IP designs. You will collaborate closely with design, verification, physical design, CAD, product engineering, and test engineering teams to deliver robust, high-coverage, production-ready IP.
Be part of a collaborative team delivering advanced IP used across SoCs.
The successful candidate brings analytical and problem-solving skills, attention to technical quality, and the ability to lead complex technical work with appropriate autonomy and cross-functional collaboration. The candidate should be able to contribute directly to technical implementation while providing technical leadership across architecture, methodology, RTL implementation, verification, and silicon debug.
The Circuit Technology team is looking for an experienced DFT/DFx Methodology, Architecture, and RTL Execution Lead to support high-speed SerDes PHYs, next-generation Memory PHYs, and die-to-die interconnect IPs.
In this role, you will own and lead DFT/DFx architecture definition, RTL implementation, methodology development, scan integration support, test constraints, ATPG support, and post-silicon debug for advanced PHY and connectivity IP designs. You will collaborate closely with design, verification, physical design, CAD, product engineering, and test engineering teams to deliver robust, high-coverage, production-ready IP.
Be part of a collaborative team delivering advanced IP used across SoCs.
The successful candidate brings analytical and problem-solving skills, attention to technical quality, and the ability to lead complex technical work with appropriate autonomy and cross-functional collaboration. The candidate should be able to contribute directly to technical implementation while providing technical leadership across architecture, methodology, RTL implementation, verification, and silicon debug.
LAYIQ is an independent job-discovery service. This listing does not imply a partnership with or endorsement by the employer. Review the original posting for current details and availability.
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