Responsibilities
- Fellow, Memory Validation Technical Lead
THE TEAM
Our Server Memory Validation team ensures the quality, reliability, and readiness of the memory subsystem across AMD server products. The team partners with architecture, silicon design, firmware, customers, and memory ecosystem partners to develop and execute validation strategies that enable industry-leading server solutions.
The team develops validation methodologies, automation, tools, and debug capabilities to improve test efficiency, failure analysis, and coverage. From pre-silicon planning through first-silicon bring-up and customer launch, the team drives memory validation readiness and execution across the product lifecycle.
THE PERSON
The Fellow, Memory Validation Technical Lead combines deep technical expertise with strong business acumen and leadership skills. The ideal candidate has extensive experience in memory architecture, server silicon validation, and post-silicon program ownership, with a proven commitment to delivering exceptional product quality.
This highly visible role requires executive-level communication, sound decision-making, and the ability to lead cross-functional teams with a focus on execution, innovation, and customer success.
THE ROLE
Drive system memory validation strategy from pre-silicon development through customer deployment across multiple memory technologies.
Ensure comprehensive validation coverage for memory subsystem functionality, power, performance, and RAS features.
Develop test strategies that uncover complex design and architecture issues while accelerating root-cause analysis.
Partner with customers and memory vendors to enable new technologies and resolve critical memory issues.
Define scalable, automation-driven validation frameworks that improve efficiency and coverage.
Lead automation priorities and validation requirements to support product milestones and launch readiness.
Serve as the technical lead for critical memory debug efforts, driving issue resolution and continuous improvements in debug methodologies and on-chip capabilities.
Leverage AI-based tools and techniques to enhance validation, analysis, and debug productivity.
EXPERIENCE
Expert knowledge of DDR, LPDDR, HBM, and memory subsystem architecture.
Extensive experience in pre-silicon and post-silicon memory validation, bring-up, debug, and performance optimization.
Strong understanding of memory RAS features, including ECC, sparing, patrol scrub, interleaving, and addressing schemes.
Deep knowledge of firmware, BIOS/UEFI, and system software interactions with memory subsystems.
Hands-on experience with SoC and system-level silicon bring-up and memory debug.
Proficiency in C, C++, Python, or similar programming and scripting languages.
Demonstrated ability to lead cross-functional teams and influence decisions across design, firmware, validation, customers, and ecosystem partners.
Excellent communication, leadership, and analytical problem-solving skills.
EDUCATION
Bachelor’s degree in Electrical Engineering/Computer Engineering/Computer Science required; Master’s degree preferred.
LOCATION
Austin, TX
Santa Clara, CA
Folsom, CA
This role is not eligible for visa sponsorship.
Qualifications
