Senior CMP Process engineer

About Samsung Austin Semiconductor

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Position Summary

A CMP (Chemical Mechanical Polishing) Process Engineer is responsible for the critical semiconductor manufacturing step of planarizing the wafer surface. This is achieved through a synergistic combination of chemical reactions and mechanical force, ensuring that subsequent layers of the chip can be built with high precision. The primary goal of a CMP engineer is to achieve a flat wafer surface by controlling the chemical reaction and mechanical force.

Role and Responsibilities

Here's What You'll Be Responsible For:

Removal Rate (RR) Control: Conducting performance evaluations of various influence factors to ensure the thickness skew before and after CMP is consistent across the entire wafer.

Condition Optimization: Determining the optimal process conditions to improve uniformity and resolve chronic issues, such as "center low RR profiles.

Recipe Management: Developing and optimizing Recipe (RCP) parameters and improve flatness.

Defect & uniformity Management: Managing and improving wafer uniformity and resolving defects such as scratches and particles.

Consumable Life Cycle Management: Monitoring the usage cycles of consumables (pads, slurry) to ensure they do not exceed specifications, which could impact quality.

Material Evaluation: Evaluating the performance of different slurries and polishing pads to optimize the CMP process.

Skills and Qualifications

Here's What You'll Need:

Basic requirement

Basic CMP Knowledge: Understanding of dielectric and metal CMP fundamentals, including slurry-pad-conditioning interactions and post-clean steps.

Prefer to have some level of Equipment Familiarities: Hands-on experience with major industry CMP tools: AMAT/EBara and their end point systems

Data & Statistics: Proficiency in Statistical Process Control (SPC), Fault Detection and Classification (FDC), and analysis software like JMP or Spotfire.

Problem Solving: Ability to drive root-cause analysis using methodologies like FMEA, 8D, and first-principles physics approaches.

Flexibility: As per business needs, sometimes it is required to work during off-hour times and/or with CWW shift schedule.

Preferred Qualifications

Familiar with Metrology Tools: Experience with Ellipsometry, SEM, and AFM for thickness and roughness check.

Experience on Defect Reduction: Experience identifying killer defects and improving wafer yield.

Basic Idea of Fab Integration: Understanding of how CMP affects following steps (Etch/Photo) and overall yield.

DOE: Ability to run structured Design of Experiments for process optimization.

The current base salary range for this role is between $106,000 - $145,000. Individual base pay rates will depend on factors including duties, work location, education, skills, qualifications and experience. Total compensation for this position will include a competitive benefits package and may include participation in company incentive compensation programs, which are based on factors to include organizational and individual performance.

This position may include access to controlled information or technology under U.S. export control laws. Employment may be contingent on either the applicant verifying that the applicant falls under the “U.S. Person” definition (including U.S. citizens, U.S. lawful permanent residents, and those granted U.S. asylum or refugee status) or the employer timely obtaining any necessary export license under federal law.

The employer evaluates export licensing on a case-by-case basis and may decline to proceed with a job applicant in its sole discretion, as export license applications can take many weeks to process.