Responsibilities
HE ROLE:
We are seeking a seasoned technical contributor that drives end-to-end delivery of PIC solutions, directly contributing to and coordinating implementation and optimization across multiple teams for optical IO deployed in next generation AI and HPC applications. The position will involve interfacing with hardware engineering teams and AMD partners to plan, develop and optimize PIC solutions. This is an exciting opportunity to work on the cutting edge of next generation GPU Computing.
THE PERSON:
You have had significant success driving photonic PDK, device, & circuit design. You are meticulous about both DFx and software while driving schedule and managing cost. You are a subject matter expert and strong technical contributor with PIC theory, design, layout, simulation, packaging, debug, test, manufacturing, reliability, qualification and support. You excel as part of a team where communication and team skills are highly valued.
K
EY RESPONSIBLITIES:
Development of OE systems in advanced Si photonics process technologies for DWDM and CWDM applications in next generation AI and HPC applications.
Innovation, product definition and specification of PIC architectures, TX chains, RX chains, components and test methodologies to meet demanding next generation Optical IO applications.
Work with systems teams to devise, maintain, simulate and optimize Optical IO link budgets reflecting key product requirements, PIC architectures, channel properties, active device component and passive component limits as well as foundry process technology capabilities.
Collaborate on design-for-test best practices to ensure that photonic devices will be ready for high-volume manufacturing.
Participate in design reviews as a subject matter expert in silicon photonic component design.
Work cross functionally with EIC, packaging, foundry technology, test development, and product teams to architect appropriate design and test automation solutions.
P
REFERRED EXPERIENCE:
Experience developing PICs that have reached HVM, from concept to field failure analysis.
Subject matter expertise in silicon photonics foundry technology, device design, and circuit layout, including FDTD/MODE/other related design tools..
Proficient in software architecture and development for photonic design automation, test automation, and data analysis. Python and Cadence development experience is preferred.
Experience in photonic wafer-, die-, and package-level testing and related test instrumentation.
Excellent communication, management, and presentation skills.
Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies
ACADEMIC CREDENTIALS:
Masters or PhD degree in Applied Physics/Electrical Engineering/or related discipline.
LOCATION:
San Jose, US
This role is not eligible for visa sponsorship.
Qualifications
